1. Field of the Invention
The present invention relates, in general, to a ball grid array substrate and a method of fabricating the same and, more particularly, to a ball grid array substrate having a window, in which the window is formed on a core material instead of using a thin core material, and in which a semiconductor chip is mounted thereon, thereby reducing the thickness of a package, and a method of fabricating the same.
2. Description of the Prior Art
In accordance with the recent trend toward a light, slim, short, and miniaturized package for semiconductor chips, a thickness of the package for semiconductor chips has been gradually reduced. Additionally, reduction of the thickness of a ball grid array substrate, on which the semiconductor chips are mounted, is needed.
Having been developed to satisfy the demand for highly integrated semiconductor chips and multiple pins, a ball grid array package belongs to an SMT-type package (surface mounting technology) which includes a plurality of conductive balls, for example, solder balls, arranged in a predetermined form on a lower side of a main board so as to be mounted on the main board.
In the ball grid array as described above, the solder balls on the ball grid array substrate are electrically attached to conductive connection patterns of a printed circuit board so as to achieve the mounting. The ball grid array is an SMT-type package in which soldering balls are arrayed instead of a lead on a backside of the printed circuit board. The ball grid array is a semiconductor chip, in which a highly integrated circuit (LSI) chip is mounted on a surface of a printed circuit board and the resulting board is sealed using a mold resin or a pot, and put in a package for multiple pin LSIs having 200 or more pins. This is also called PAC (pad array carrier), and is advantageous in that it is possible to fabricate a main body of the package so that the main body is smaller than a QFP (quad flat package) which is provided with L-shaped lead pins protruding from four sides thereof.
Accordingly, with respect to recent packages, such as MCMs (multi-chip packages) and SIPs (system in packages), on which semiconductor chips are stacked, a thin core material is used to make a ball grid array substrate slim.
FIGS. 1a to 1j are sectional views illustrating the fabrication of a ball grid array substrate according to an embodiment of a conventional technology.
As shown in FIG. 1a, a copper clad laminate (CCL), which includes an insulating resin layer 101 and copper foils 102a, 102b on both sides of the insulating resin layer, is prepared as a substrate 100.
As shown in FIG. 1b, via holes (A) are formed to connect circuits of the upper and lower copper foils 102a, 102b of the substrate 100 to each other.
As shown in FIG. 1c, copper plating layers 103a, 103b are formed on the upper and lower copper foils 102a, 102b of the substrate 100 and on walls of the via holes (A) so as to electrically connect the via holes (A).
As shown in FIG. 1d, dry films 104a, 104b are layered on the upper and lower copper plating layers 103a, 103b of the substrate 100.
As shown in FIG. 1e, the dry films 104a, 104b having a predetermined pattern are exposed and developed. The predetermined pattern includes a circuit pattern, lands of the via holes (A), a wire bonding pad pattern, and a solder ball pad pattern.
As shown in FIG. 1f, the dry films 104a, 104b having the predetermined pattern are used as an etching resist, and the substrate 100 is dipped in an etchant, thereby etching portions of the upper and lower copper foils 102a, 102b and the copper plating layers 103a, 103b, which do not correspond in position to the predetermined pattern of the dry films 104a, 104b, to remove them.
As shown in FIG. 1g, the dry films 104a, 104b are stripped from upper and lower sides of the substrate 100, and are thus removed.
As shown in FIG. 1h, solder resists 105a, 105b are applied on the substrate 100, and then subjected to a pseudo-drying process.
As shown in FIG. 1i, the upper and lower solder resists 105a, 105b are exposed and developed to cure portions of the solder resists 105a, 105b, in areas corresponding to patterns of the solder resists. Subsequently, uncured portions of the solder resists are removed to pattern the solder resists 105a, 105b. 
As shown in FIG. 1j, a gold plating layer 106a is formed on a wire bonding pad, which has a position corresponding to an opening (B) of the upper solder resist 105a of the substrate 100, and a gold plating layer 106b is formed on a solder ball pad, which has a position corresponding to an opening (C) of the lower solder resist 105b of the substrate 100.
FIG. 2 is a sectional view of a product, in which a semiconductor chip is mounted on a ball grid array board, fabricated according to the procedure of FIGS. 1a to 1j. 
As shown in FIG. 2, after a semiconductor chip 220 is mounted using an adhesive 210 and a wire bond 230 and a solder ball 240 are formed, a molding 250 is formed, thereby creating the product in which the semiconductor chip is mounted on the ball grid array package substrate.
The fabrication of the ball grid array substrate as described above is disclosed in Korean Pat. No. 344,618, which was filed on Dec. 15, 1999 by the applicant of the present invention.
The above conventional technology has a disadvantage in that the package is thick.
Furthermore, the conventional technology is problematic in that since a thin core material is employed, investment is required to move the thin core material.
The conventional technology is also problematic in that a carrier is required to handle the thin material in a package assembly process.
FIG. 3 illustrates a product, in which a semiconductor chip is mounted on a ball grid array substrate, according to another embodiment of the conventional technology.
As shown in FIG. 3, after a cavity is formed through a substrate 300 in which circuit patterns 304 are formed on both sides of an insulator 301, a semiconductor chip 305 is mounted in the cavity. Subsequently, a wire bonding pad is connected to a semiconductor chip through wire bonds 303, and solder balls 302 are mounted on solder ball pads. Finally, the ball grid array substrate is packaged, thereby creating the product.
The fabrication of the ball grid array substrate as described above is disclosed in U.S. Pat. No. 5,696,666.
The above conventional technology is problematic in that heat, generated from the semiconductor chip 305, is emitted only through the wire bonds 303 but not through the insulator 301 having no thermal conductivity, thus heat radiation is low.